Sintered Metal Flip Chip Joints

ABSTRACT

An integrated circuit die may be fabricating to have a plurality of contacts. A metal post may be formed on each of the plurality of contacts. A plurality of bumps may be formed on a plurality of contact regions of a leadframe or on the posts, in which the plurality of bumps are formed with a material that includes metal nanoparticles. The IC die may be attached to the leadframe by aligning the metal posts to the leadframe and sintering the metal nanoparticles in the plurality of bumps to form a sintered metal bond between each metal post and corresponding contact region of the leadframe.

FIELD OF THE INVENTION

This disclosure relates to bonding metal contact posts of asemiconductor die to a metal leadframe in a flip chip configuration, andin particular to using sintered metal to form a solder free bond betweenthe metal posts on the die and the leadframe.

BACKGROUND OF THE INVENTION

Flip chip is a method for interconnecting semiconductor devices, such asIC chips and micro-electromechanical systems (MEMS), to externalcircuitry with solder bumps that have been deposited onto the chip pads.The solder bumps are deposited on the chip pads on the top side of thewafer during the final wafer processing step. In order to mount the chipto external circuitry (e.g., a circuit board or another chip or wafer),it is flipped over so that its top side faces down, and aligned so thatits pads align with matching pads on the external circuit or leadframe,and then the solder is reflowed to complete the interconnect. This is incontrast to wire bonding, in which the chip is mounted upright and wiresare used to interconnect the chip pads to external circuitry or leadframe.

Processing a flip chip is similar to conventional IC fabrication, with afew additional steps. Near the end of the manufacturing process, theattachment pads are metalized to make them more receptive to solder.This typically consists of several treatments. More recently, a processis used in which metal posts are formed on each metalized attachment patto extend the height of the contact. A small dot of solder is thendeposited on each metalized pad. Alternatively, the solder dots may beplaced on the leadframe. The chips are then cut out of the wafer asnormal.

To attach the flip chip into a circuit, the chip is inverted to bringthe solder dots down onto connectors on the underlying leadframe orcircuit board. The solder is then re-melted to produce an electricalconnection, typically using a Thermosonic bonding or alternatively areflow solder process.

BRIEF DESCRIPTION OF THE DRAWINGS

Particular embodiments in accordance with the invention will now bedescribed, by way of example only, and with reference to theaccompanying drawings:

FIG. 1 is a cross section of a prior art flip chip joint using solder;

FIGS. 2A-2G are a series of cross sectional views illustrating formationof a flip chip sintered metal joint;

FIG. 3 is a plot illustrating melting point vs. particle size in asintering process;

FIGS. 4A-4D are a series of cross sectional views of another embodimentin which a sintered metal bond is formed;

FIG. 5 is a cross sectional view of a completed integrated circuit;

FIG. 6 is an illustration of a portion of a leadframe strip;

FIGS. 7A-7B illustrate another embodiment for forming posts; and

FIG. 8 is an illustration of multiple IC dies mounted to a substrateusing sintered metal bonds.

Other features of the present embodiments will be apparent from theaccompanying drawings and from the detailed description that follows.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Specific embodiments of the invention will now be described in detailwith reference to the accompanying figures. Like elements in the variousfigures are denoted by like reference numerals for consistency. In thefollowing detailed description of embodiments of the invention, numerousspecific details are set forth in order to provide a more thoroughunderstanding of the invention. However, it will be apparent to one ofordinary skill in the art that the invention may be practiced withoutthese specific details. In other instances, well-known features have notbeen described in detail to avoid unnecessarily complicating thedescription.

Current FCOL (flip chip on leadframe) products typically use a solderalloy to bond metallic posts formed on the semiconductor die onto aleadframe. Typically, the posts are copper (Cu) and range in size from75 um circular to 100×300 um oval. Typically, the leadframe is copper.While a solder bond provides a good connection between the copper postsand copper leadframe, there are known solder joint quality/reliabilityissues. For example, infant mortality failures may occur due to voidingfrom the flux or the solder paste process. The adoption of lead (Pb)free solder by the industry has resulted in a more brittle solder.Thermally driven void development and growth may occur under thermalaging. Solder joint cracking may occur under temperature cycling.Additionally, the current carrying capacity of a solder joint may beless than optimum.

An improved process for producing a FCOL device will now be disclosed.An embodiment of this disclosure may print a metallic nanoparticleloaded solution onto the flip chip bumps or target substrate pads thatwill connect the two surfaces and be fused to form a solidmetal-to-metal connection. This may result in a bond that increases themaximum current allowed in a flip chip package. This process may improvejoint cracking that has resulted from brittle Pb-free solder. Thisimproved process may also prevent solder voiding during assembly andreliability stress.

FIG. 1 is a cross section of a prior art flip chip 102 with an exemplarysolder joint. At each contact region of semiconductor die 102, a metallayer 103, referred to as a “copper over anything” (COA) layer, may bedeposited and then patterned to form a metalized contact region 103. Ametallic post 104 is formed in contact with the metalized contact region103. A solder dot 105 may be placed on either the post 104 or aleadframe 106 and then heated to form a solder bond between post 104 andleadframe 106 using a Thermosonic or reflow process, for example. Noticethat the solder forms a layer between post 104 and leadframe 106 andthereby may limit current capacity through post 104 to or from circuitryon die 102. Furthermore, as mentioned above, if the solder is Pb freesolder, then there may be a tendency for a crack to form betweenleadframe 106 and post 104 due to thermal cycling.

FIGS. 2A-2G are a series of cross sectional views illustrating formationof a flip chip sintered metal joint. In FIG. 2A, a small portion of asemiconductor die 202 is illustrated. It is to be understood that die202 may extend to the left and to the right to include various circuitryand multiple contact regions, as is well known in the art. In thisillustration, only a single contact region 207 is illustrated. On top ofcontact region 207, a COA copper layer has been deposited to form metalfeature 203 that is in contact with contact region 207. COA layer 203may be applied by sputtering, for example. A photo resist layer may thenbe applied and patterned to allow post 204 to be formed byelectroplating, for example. The photo resist may then be removed toreveal post 204 extending from the surface of die 202.

FIG. 2B illustrates an inkjet printer 210 depositing a series ofdroplets 211 that contain metal nanoparticles onto the metal post 204.Fabrication of three dimensional structures using ink jet printers orsimilar printers that can “print” various polymer materials is wellknown and need not be described in further detail herein. For example,see “3D printing,” Wikipedia, Sep. 4, 2014. Printing allows for therapid and low-cost deposition of thick dielectric and metallic layers,such as 0.1 um-1000 um thick, for example, while also allowing for finefeature sizes, such as 20 um feature sizes, for example.

The ink may include a solvent or several solvents to match rheology andsurface tension, and metallic nanoparticles. The size of thenanoparticle may be in a range of 2-100 nm, for example. The ink mayalso include a dispersant such as polyvinylpyrrolidone (PVP) or becharge dispersed to prevent agglomeration of the particles. The ink mayalso include binders such as polymer epoxies, and other known or laterdeveloped ink additives.

The film residue that is left from the ink may then be cured in the caseof solvent or dispersant based ink where solvent or dispersant isevaporated. Curing may be thermal (50-250 C), UV, Infrared, Flash Lamp,or of another form that is compatible with the ink being used.

In this example, the metal nanoparticles may be copper, or a mixture ofcopper and silver, for example. In another embodiment, the nanoparticlesmay be a mixture of copper and graphene, or copper and graphite, forexample. The graphite/grapheme mixtures allow for a higher currentdensity without electromigration. In another embodiment, thenanoparticles may be copper oxide that is later reduced back copperduring a sintering step that will be described in more detail below. Inanother embodiment, the nanoparticles may be selected to bond to a metalpost formed from a different metal than copper, for example.

FIGS. 2C-2D illustrate how a “bead” or a “bump” 212 may build up on thetop of metal post 204 formed from multiple droplets 211 dispensed frominkjet printer 210.

FIGS. 2E-2F illustrate how die 202 may be “flipped” and positioned overa leadframe 220. Leadframe 220 will typically have a set of leads, eachof which has a contact region 221. Each post 204 is designed to alignwith a particular contact region 221. In these figures, only a smallpart of leadframe 220 is shown for clarity. The design and fabricationof leadframes is well known and need not be described in detail herein.Once the flipped die 202 is aligned with leadframe 220, it may belowered so that each post 204 and bump 212 is brought into contact witheach corresponding contact region 221.

FIG. 2F illustrates the result of a sintering process in which the bump212 that is formed by metal nanoparticles is converted into a solidstructure 213. Sintering is the process of compacting and forming asolid mass of material by heat and/or pressure without melting it to thepoint of liquefaction. The atoms in the materials may diffuse across theboundaries of the particles, fusing the particles together and creatingone solid piece. Typically, the sintering temperature does not have toreach the melting point of the material; therefore sintering is oftenchosen as the shaping process for materials with extremely high meltingpoints. Most, if not all, metals can be sintered. This appliesespecially to pure metals produced in vacuum which suffer no surfacecontamination.

Sintering the nanoparticles of bump 212 produces a solid structure 213that forms a sintered metal bond between post 204 and contact region 221of leadframe 220. Adhesion of the sintered metal to the metal surface ofthe post and lead frame may occur in three manners: (1) van der Waalsforces, (2) mechanical adhesion/roughness, (3) through the nanoparticleor lead frame surface chemical diffusion into the other. Unlike a jointformed by eutectic solder, sintered metal bond 213 will not melt anddegrade the bond if the die is heated a second time.

Each sintered metal bond is typically porous as a result of spaces thatremain between the nanoparticles after the sintering process. However, asintering process may be continued until porosity is reduced oreliminated. A porous sintered bond may reduce thermo-mechanicalreliability risk due to an ability to flex in response to stress appliedto the bond by thermal or mechanical forces. The amount of porosity maybe controlled by controlling one or more aspects of the sinteringprocess, such as: selecting the size of the nanoparticles, selecting thetemperature profile or other process parameters used to perform thesintering process, etc. Another way to control porosity is to add asacrificial nanoparticle to the ink, such as poly-methyl methacrylate,or other polymer, silica, etc; then remove these particles during thesintering or after the sintering to increase the porosity. A typicalnanoparticle sintered metal bond may have a porosity of approximately20%. Generally, porosity may be selected to fall within a range of0%-50% while still providing good current carrying capacity andstructural integrity.

Sintering may be performed in a number of ways. For example, the partsmay be heated to an elevated temperature but need not be heated to themelting point of the metal that forms the nanoparticles. For example,copper nanoparticles may be heated to a range of 80-300 C to form asolid structure. For comparison, the melting point of copper is 1,085 C.

FIG. 3 is a plot illustrating melting point vs. particle size for coppernanoparticles in a sintering process. The small nanoparticles may melttogether at very low temperatures; however, as they melt together theyget larger which causes the “bulk” melting temperature of thenanopartilces to go up. This causes an irreversible process in whichhigher temperature will only make the particles get bigger and thus meltat an even higher temperature. Thus, once the small nanoparticles aremelted, the resulting structure cannot be un-melted like solder, unlessthe melting point of the bulk metal is reached. Note in FIG. 3, whilesintering may occur at a temperature range of 80-300 C for coppernanoparticles, the resulting sintered metal bond cannot be re-meltedunless the temperature of the sintered metal structure is raised to 1085C, which is the melting point of bulk copper.

In another embodiment, copper oxide nanoparticles, for example, may besintered using a Xenon flash lamp using a known or later developedphoton sintering process.

In another embodiment, copper oxide nanoparticles, for example, may besintered in a reducing atmosphere using a known or later developedforming gas or formic acid sintering process. In this case, the copperoxide is converted back to pure copper by the formic acid process.Typically, this process may be performed at a temperature in the rangeof 200-250 C.

FIGS. 4A-4D are a series of cross sectional views of another embodimentin which a sintered metal bond is formed. In this embodiment, a bump 412may be formed on each contact region of leadframe 420 by depositing aseries of droplets 411 that contain metal nanoparticles onto the contactregion 421 of leadframe 420 by an inkjet printer 210. As describedabove, the metal nanoparticles may be copper, or a mixture of copper andsilver, or other metals, for example. In another embodiment, thenanoparticles may be a mixture of copper and graphene, or copper andgraphite, for example. The graphite/grapheme mixtures allow for a highercurrent density without electromigration. In another embodiment, thenanoparticles may be copper oxide that is later reduced back copperduring a sintering step that will be described in more detail below. Inanother embodiment, the nanoparticles may be selected to bond to a metalpost formed from a different metal than copper, for example.

FIG. 4C illustrates how die 402 may be “flipped” and positioned overleadframe 420. Die 402 may be similar to die 202 with a post 404 formedon each contact region of die 402 as described above in more detail.Leadframe 420 will typically have a set of leads, each of which has acontact region 421. Each post 404 is designed to align with a particularcontact region 421. In these figures, only a small part of leadframe 420is shown for clarity. The design and fabrication of leadframes is wellknown and need not be described in detail herein. Once the flipped die402 is aligned with leadframe 420, it may be lowered so that each post404 is brought into contact with each corresponding bump 412 on contactregion 421.

FIG. 4D illustrates the result of a sintering process in which the bump412 that is formed by metal nanoparticles is converted into a solidstructure 413. As described above, sintering is the process ofcompacting and forming a solid mass of material by heat and/or pressurewithout melting it to the point of liquefaction. Sintering thenanoparticles of bump 412 produces a solid structure 413 that forms asintered metal bond between post 404 and contact region 421 of leadframe420. Unlike a joint formed by eutectic solder, sintered metal bond 413will not melt and ruin the bond if the die is heated a second time.

FIG. 5 is a cross sectional view of a completed integrated circuit 500.Integrated circuit 500 may be formed using the sintered metal bondingprocess described in either FIG. 2A-2G or 4A-4D. Semiconductor die 502includes circuitry that may be connected to a plurality of contact padson which is formed a plurality of metal posts 504. A plurality of bumpsmay be formed on a plurality of contact regions of leadframe 520 or onthe posts 504, in which the plurality of bumps are formed with amaterial that includes metal nanoparticles. IC die 502 may be attachedto leadframe 520 by aligning the metal posts 504 to the leadframe andsintering the metal nanoparticles in the plurality of bumps to form asintered metal bond between each metal post and contact region of theleadframe, as described above in more detail.

In another embodiment, a portion of the plurality of bumps may be formedon a portion of the posts and another portion of the plurality of bumpsmay be formed on a portion of the contact regions of the leadframe, forexample.

Once die 502 is attached to leadframe 520, a molding process may beperformed to encapsulate the die and leadframe to form finished IC 500.The process of encapsulation is well known and need not be describedherein.

Finished IC 500 may be mounted on a substrate, such as a fiberglassprinted circuit board, a ceramic circuit board, or any other known orlater developed type of single layer or multilayer system substrate onwhich are formed various signal traces. Other ICs and electroniccomponents may also be mounted on the substrate to form an electronicdevice or system, for example.

Some integrated circuits have no-lead packages such as quad-flatno-leads (QFN) and dual-flat no-leads (DFN) devices that physically andelectrically couple integrated circuits to printed circuit boards. Flatno-lead devices, also known as micro leadframe (MLF) and small outlineno-leads (SON) devices are based on a surface-mount technology thatconnects integrated circuits to the surfaces of printed circuit boardswithout through-holes in the printed circuit boards. In some examples,flat no-lead packages are near chip scale plastic encapsulated packagestypically fabricated with a planar copper leadframe substrate. Perimeterlands on the package provide electrical coupling to the printed circuitboard. The lands serve as contacts and may be referred to as leadsinternal to the integrated circuit; however, the leads do not extendbeyond the boundaries of the integrated circuit package.

FIG. 6 is an illustration of a portion of a leadframe strip 600 thatillustrates four repetitions of a leadframe 620. Each leadframe 620includes a set of leads, such as lead 622, that may transition into acorresponding set of pins, such as pin 623. Each lead has a contactregion 621 that is intended to align with a post on a semiconductor die.As described above in more detail, dots of metallic nanoparticlematerial may be added to each contact region 621 on each leadframe 620by an inkjet process, for example. Alternatively, another additiveprocess may be used to create the metallic nanoparticle bumps, such as:screen printing, electrostatic spraying, etc.

In this manner, an IC may be fabricated and attached to a leadframe inwhich sintered metal bonds are formed between the contacts on the IC dieand the contact regions of the leadframe. Sintering may be performed ata temperature that is much lower than the melting point of the metalnanoparticles being use. This allows the use of organic substrates forthe leadframe structure or other substrate structure, for example, thatwould not withstand a higher temperature process.

A sufficient volume of nanoparticle material may be printed for eachbump in order to compensate for expected non-coplanarity of the die tosubstrate surface.

Sintering eliminates the problem of intermetallic growth between copperand tin-based Pb-free solder. Brittle solder fatigue and thermallyactivated void growth in solder may be eliminated by the sintered metalbond. Current carrying capacity of the joint may also be enhanced.

Other Embodiments

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various other embodiments of the invention will beapparent to persons skilled in the art upon reference to thisdescription. For example, while copper posts and leadframes weredescribed herein, other embodiments may use other types of metal for theposts and/or leadframes, such as aluminum, gold, nickel, etc.

Different metallic nanoparticles may be used in various embodiments,such as: copper, copper-silver hybrid, copper oxide, copper graphite,copper graphene, etc.

FIGS. 7A-7B illustrate another embodiment for forming posts. Whileprinting of a nanoparticle bump on top of a solid metal post wasdescribed herein, in another embodiment the entire post, or asignificant portion of the post may be formed by inkjet printing thenanoparticle material, for example. In FIG. 7A, a small portion of asemiconductor die 702 is illustrated. It is to be understood that die702 may extend to the left and to the right to include various circuitryand multiple contact regions, as is well known in the art. In thisillustration, only a single contact region 707 is illustrated. On top ofcontact region 707, a COA copper layer has been deposited to form metalfeature 703 that is in contact with contact region 707. COA layer 703may be applied by sputtering, for example. A photo resist layer may thenbe applied and patterned to form metal region 703.

A stream of ink droplets 711 may then be applied to metal region 703 byinkjet printer 210 to form a metallic post 704. After die 702 isattached to a leadframe or other substrate, a sintering process asdescribed above may be used to convert post 704 into a solid sinteredmetal post that is bonded to the leadframe, as described above in moredetail.

FIG. 8 is an illustration of two semiconductor dies 801, 802 mounted toa multilayer substrate 840. While mounting a semiconductor die to astamped or etched metal leadframe was illustrated herein, in otherembodiments the leadframe may be a multilayer substrate that has contactareas patterned onto it, for example. In such an embodiment, thesubstrate 840 may extend beyond the semiconductor die and there may betwo or more ICs and/or other electronic components mounted on thesubstrate. The substrate may be a fiberglass printed circuit board, aceramic circuit board, or any other known or later developed type ofsingle layer or multilayer system substrate on which are formed varioussignal traces, for example. In this case, nanoparticle bumps such asbumps 841, 842 may be formed on each of the dies as described withregard to FIGS. 2A-2D, or may be formed on the substrate as describedwith respect to FIGS. 4A-4B, for example. After the dies 801, 802 aremounted on substrate 840, all of the nanoparticle bumps may be sinteredas described above in a single operation to form sintered metal bondsbetween the contact regions on the substrate and the contact posts onthe dies.

While embodiments disclosed herein refer to flip chip configurations,other embodiments may be formed using sintered metal bonds, such as:stacked dies, dies with through silicon vias, etc.

Certain terms are used throughout the description and the claims torefer to particular system components. As one skilled in the art willappreciate, components in digital systems may be referred to bydifferent names and/or may be combined in ways not shown herein withoutdeparting from the described functionality. This document does notintend to distinguish between components that differ in name but notfunction. In the following discussion and in the claims, the terms“including” and “comprising” are used in an open-ended fashion, and thusshould be interpreted to mean “including, but not limited to . . . .”Also, the term “couple” and derivatives thereof are intended to mean anindirect, direct, optical, and/or wireless electrical connection. Thus,if a first device couples to a second device, that connection may bethrough a direct electrical connection, through an indirect electricalconnection via other devices and connections, through an opticalelectrical connection, and/or through a wireless electrical connection.

Although method steps may be presented and described herein in asequential fashion, one or more of the steps shown and described may beomitted, repeated, performed concurrently, and/or performed in adifferent order than the order shown in the figures and/or describedherein. Accordingly, embodiments of the invention should not beconsidered limited to the specific ordering of steps shown in thefigures and/or described herein.

It is therefore contemplated that the appended claims will cover anysuch modifications of the embodiments as fall within the true scope andspirit of the invention.

What is claimed is:
 1. A method for fabricating an integrated circuit,the method comprising: fabricating an integrated circuit (IC) die havinga plurality of contacts; forming a metal post on each of the pluralityof contacts; forming a plurality of bumps on a plurality of contactregions of a leadframe or on the posts, in which the plurality of bumpsare formed with a material that includes metal nanoparticles; andattaching the IC die to the leadframe by aligning the metal posts to theleadframe and sintering the metal nanoparticles in the plurality ofbumps to form a sintered metal bond between each metal post andcorresponding contact region of the leadframe.
 2. The method of claim 1,in which the sintering the metal nanoparticles forms a sintered metalbond that is porous.
 3. The method of claim 2, in which the sinteredmetal bond has a porosity ranging from 0%-50%.
 4. The method of claim 1,in which a portion of the plurality of bumps is formed on a portion ofthe posts and another portion of the plurality of bumps is formed on aportion of the contact regions of the leadframe.
 5. The method of claim1, in which forming the plurality of bumps is done by printing with aninkjet printer.
 6. The method of claim 1, in which forming a metal postis done by printing with an inkjet printer.
 7. The method of claim 1, inwhich sintering the metal nanoparticles is done by heating, by use of aXenon flash tube, or by use of Formic acid.
 8. The method of claim 1, inwhich the metal nanoparticles include copper nanoparticles and silvernanoparticles.
 9. The method of claim 1, in which the metalnanoparticles include copper oxide nanoparticles.
 10. The method ofclaim 1, in which the metal nanoparticles include copper nanoparticlesand graphite nanoparticles.
 11. An integrated circuit comprising: anintegrated circuit (IC) die with a plurality of contacts, in which ametal post is formed on each of the plurality of contacts; and aleadframe, in which a plurality of contact regions on the lead frame arealigned with the plurality of contacts and metal posts and coupledthereto by sintered metal bonds.
 12. The IC of claim 11, in which thesintered metal bonds are porous.
 13. The IC of claim 12, in which thesintered metal bond has a porosity ranging from 0%-50%.
 14. The IC ofclaim 11, in which the sintered metal bonds include copper nanoparticlesand silver nanoparticles.
 15. The IC of claim 11, in which the sinteredmetal bonds include copper oxide nanoparticles.
 16. The IC of claim 11,in which the sintered metal bonds include copper nanoparticles andgraphite nanoparticles.
 17. An integrated circuit leadframe comprising:a plurality of leads configured to couple to a plurality of contacts onan integrated circuit die; and a plurality of bumps formed on theplurality of leads configured to align with the plurality of contacts onthe integrated circuit die, in which the bumps are formed with amaterial that includes metal nanoparticles.
 18. The leadframe of claim17, in which the leadframe is a multi-layer substrate.
 19. The leadframeof claim 17, in which the bumps have been sintered to form sinteredmetal bonds that are porous.
 20. The leadframe of claim 17, in which themetal nanoparticles include copper nanoparticles and silvernanoparticles; copper oxide nanoparticles; or copper nanoparticles andgraphite nanoparticles.